1. Field of the Invention
The present invention relates to electronic imaging devices and, in particular, to low-noise MOS-based imagers having minimal analog components in each pixel. The invention provides both a method and apparatus for significantly improving cancellation of reset noise in an MOS active pixel sensor (APS).
2. Description of Related Art
The prior art describes many alternatives to CCD sensors for generating video or still images. The various schemes can be grouped into two basic classes, depending upon whether signal amplification is performed at each pixel or in support circuits. In the passive-pixel sensor, pixel simplicity and optical fill factor are maximized. Active-pixel sensors (APS""s) include an amplifier at each pixel site to instead optimize signal transfer and sensitivity.
The simplest passive pixel comprises a photodiode and an access transistor wherein the photo-generated charge is passively transferred from each pixel to downstream circuits. The integrated charge must, however, be efficiently transferred with low noise and low nonuniformity. Since each column of pixels often shares a common row or column bus for reading the signal, noise and nonuniformity suppression are typically facilitated in the xe2x80x9ccolumnxe2x80x9d buffer servicing each bus. In U.S. Pat. No. 5,043,820, Wyles teaches using a buffer amplifier with capacitive feedback to yield reasonable sensitivity considering the large bus capacitance. Since such charge-amplification means were not generally practical for on-chip implementation in early MOS imaging sensors, alternative means compatible with NMOS technology were used. One approach which as mass-produced by Hitachi for camcorders is described in xe2x80x9cMOS Area Sensor, etc . . . xe2x80x9d Parts I and IIxe2x80x9d in IEEE Trans. Electron Devices, ED-27 (8), August, 1980, pp. 1676-1687. The key refinements with respect to the transimpedance amplifier include anti-blooming control and circuitry for reducing fixed pattern noise. Though these imagers were inferior to the emerging charge coupled device (CCD) imagers available at the time, similar MOS imagers are still being offered commercially.
Subsequent efforts at improving passive-pixel imager performance have also focused on column buffer enhancements. One improvement to the column buffer involved using an enhancement/depletion inverter amplifier to provide reasonably large amplification in a small amount of real estate; its 40 lux (lx) sensitivity was nevertheless nearly an order of magnitude below that of competing CCD-based sensors. Another improvement both enhanced sensitivity and facilitated automatic gain control via charge amplification in the column buffer. Recently, those working in the art have revisited the original capacitive-feedback transimpedance amplifier (CTIA) concept because the CTIA appears to the inventors to be nearly ideal for passive-pixel readout if issues with temporal noise pickup and fixed-pattern noise are adequately addressed.
Though much progress has been made in developing passive-pixel imagers, their temporal S/N performance is fundamentally inferior to competing CCD imagers because the bus capacitance translates to read noise of ≈100 exe2x88x92. CCDs, on the other hand, typically have read noise of 20 to 40 exe2x88x92 at video frame rates. Nevertheless, the allure of producing imagers in conventional MOS fabrication technologies rather than esoteric CCD processes (which usually require many implantation steps and complex interface circuitry in the camera) has encouraged the development of active-pixel sensors that can better compete with CCDs.
It appears to the inventors that the first step in such development is to mitigate the noise associated with the bus capacitance. One approach has been to add amplification to the pixel via the phototransistor by means of a Base-Stored Image Sensor (BASIS) which uses a bipolar transistor in emitter follower configuration together with a downstream correlated double sampler to suppress random and temporal noise. By storing the photogenerated-signal on the phototransistor""s base to provide charge amplification, the minimum scene illumination was reportedly reduced to 10xe2x88x923 lx in a linear sensor array. However, the minimum scene illumination was higher (10xe2x88x922 lx) in a two-dimensional BASIS imager having 310,000 pixels because the photoresponse nonuniformity was relatively high (xe2x89xa62%). These MOS imagers had adequate sensitivity, but their pixel pitch was too large at about 13 xcexcm. It has thus appeared desirable to the inventors to shrink the pixel pitch while also reducing photoresponse nonuniformity.
Since the incorporation of bipolar phototransistors is not strictly compatible with mainstream CMOS processes, others have segregated photodetection and signal amplification in an active-pixel sensor essentially comprising a three-transistor pixel with photodiode. All such proposals still offer inadequate performance. One approach discussed in U.S. Pat. No. 5,296,696, for example, augments the basic source-follower configuration with a column buffer that cancels fixed pattern noise, but adds a fourth transistor in a manner that creates a floating node vulnerable to generation of random offsets from charge-pumping and concomitant charge redistribution. U.S. Pat. No. 5,043,820 offers a method for injecting charge to reduce offset errors, but not with adequate accuracy and resolution to be useful for competing with CCDs. Furthermore, these and other similar approaches which require 3-4 transistors in the pixel (at least one of which is relatively large to minimize amplifier l/f noise) in addition to the photodiode, also require off-chip signal processing for best S/N performance because none addresses the dominant source of temporal noise, namely the reset or xe2x80x9cKTCxe2x80x9d noise.
In order to eliminate or greatly suppress the reset (kTC) noise generated by resetting the detector capacitance, a dedicated memory element is usually needed, either on-chip or off-chip, to store the reset voltage to apply correlated double sampling by coherently subtracting the stored correlated reset noise while each pixel""s photo-generated voltage is being read. U.S. Pat. No. 5,471,515 subsequently addressed this basic deficiency by developing an APS that uses intra-pixel charge transfer to store the reset charge at each pixel at the start of each imaging frame. This floating gate APS facilitates correlated double sampling with high efficiency by adding several transistors and relying on a photogate for signal detection.
As those skilled in the art will appreciate, in conventional correlated double sampling (CDS) the reset noise is sampled, stored and later subtracted from the composite signal level. Both temporal and spatial noise are reduced since the reset noise is correlated within each frame. CDS, however, requires a storage means for each pixel that resides either on- or off-chip. Adding the memory element to each pixel compromises the pixel optical fill factor or often requires circuit elements not strictly compatible with standard CMOS processes. One alternativexe2x80x94adding the memory cell to the integrated circuitxe2x80x94greatly adds to the chip area and associated fabrication cost or increases vulnerability to blooming and lag. A second alternativexe2x80x94providing the memory in support electronicsxe2x80x94requires both full frame memory to store the reset levels on a frame-by-frame basis and signal processing electronics to digitally subtract the stored reset values.
The drawbacks of various prior art approaches are intractable because they increase imager cost. For example, the ""515 patent approach adds several transistors to each pixel and several million transistors to each imager thereby reducing production yield. The BASIS apparatus employing bipolar transistors is not compatible with standard CMOS gate fabrication so a nonstandard process must be developed. These deficiencies were subsequently addressed by Ackland U.S. Pat. Nos. 5,576,763 and 5,541,402; and by Chi in U.S. Pat. Nos. 5,587,596 and 5,608,243. Ackland addresses the image lag issues associated with the intra-pixel charge transfer means but still requires a non-standard CMOS process. Chi reduces pixel complexity at the expense of reset noise by instead using the simplest possible active pixel comprising only a phototransistor and reset MOSFET. Chi""s implementation incurs reset noise and compromises spectral response at longer wavelengths by putting the photodiode in an n-well.
The invention facilitates creation of an improved electronic imaging system and also provides an improved method and apparatus for canceling reset noise in an APS. A key feature of the invention is an integrated low-noise amplifier that provides low temporal and fixed pattern noise while simultaneously providing reasonably high optical fill factor in mature, cost-effective CMOS processes. Application of the invention facilitates construction of a video camera that can be configured as a single CMOS integrated circuit supported by only an oscillator and a battery.
Important aspects of the present invention are an improved active pixel sensor, as well as a low-noise imaging system for implementation in CMOS or in other semiconductor fabrication technologies. The low-noise amplifier system minimizes the reset noise generated by resetting the integration capacitance via a novel active pixel sensor (APS) implementation that is capable of reasonably high optical collection efficiency in xe2x89xa60.5 xcexcm CMOS. The lower noise of the active pixel sensor significantly increases the maximum attainable on-chip signal-to-noise ratio relative to the current state-of-the-art. Many current systems require either expensive off-chip memory and signal processing or alternative APS schemes which attempt to mimic charge-coupled device technology to achieve low noise. The latter schemes are typically not directly manufacturable using standard CMOS processes. The present invention can be readily manufactured in conventional CMOS processes available at many production foundries.
The new active-pixel sensor comprises a photodetector and four transistors to eliminate the reset noise which otherwise occurs. Three of the transistors can be sized using the minimum possible dimensions set by the lithography to maximize the collection area of the phototransistor. The invention obviates the otherwise ubiquitous need for conventional correlated double sampling (CDS) by effectively constructing an active-pixel comprising a photodiode, two capacitors and four transistors.
To minimize total cost and the signal processing burden for the downstream electronics while also facilitating the production of low-noise CMOS imagers with reasonably high optical fill factor and low noise, the inventors add a fourth transistor to the basic three transistor CMOS active pixel sensor to null the reset noise. Via a straightforward layout, the fourth transistor facilitates the addition of a relatively small storage capacitor, Cstore, adjacent to the photodiode and a small capacitance, Cfb, to couple the storage node to the photodiode. The small capacitive coupling provides a linear attenuation in which the programming waveform actively modifies the photodiode voltage to cancel the reset noise. Just after each pixel is reset, a feedback amplifier servicing the pixel and having a gain equal to a specified multiple of the linear attenuation factor, nulls out the noise (both temporal and FPN), and the storage capacitor is then latched. Upon readout of the photogenerated signal after the prescribed signal integration time, the xe2x80x9crawxe2x80x9d output is thus devoid of a substantial portion of the reset noise. This technique does not suffer the bandwidth limitations of other feedback-based schemes and is therefore compatible with higher row reset rates for video rate imaging of large format imagers. Also, it does not require additional memory to store each pixel""s offset voltage.
The four transistor APS of the present invention comprises a first transistor that functions as the driver of a source follower amplifier during signal readout, a second transistor which facilitates signal readout, a third transistor which serves as a reset switch and a fourth transistor to cancel the reset noise. The reset and read operations are appropriately facilitated by on-chip digital clocking logic that reads the signal from each pixel, multiplexes the signal outputs from an array of pixels, resets the pixels, and enables the array of feedback loops to cancel the imager""s reset noise on a pixel-by-pixel basis. In the typical two-dimensional array, the multiplexing is performed, as in the prior art, by horizontal and vertical shift registers. Just after all the active pixels in a row (in a one- or two-dimensional imaging array) are reset on a row-by-row basis, each column buffer cancels the selected pixel""s reset noise by appropriately modifying the photodiode voltage at the start of the integration cycle.
For a visible imager APS design, one additional transistor is needed in each pixel as compared to the basic three-transistor APS design. This requirement compromises the optical fill factor, but to a much smaller degree than if an optimally sized CDS capacitor were used instead. In addition, since the gate-to-source capacitance of the nulling xe2x80x9cfourthxe2x80x9d transistor is used, and since this capacitance is formed by increasing the gate-to-source overlap via the thin gate oxide, the necessary real estate is small. The required area is further reduced as compared to that required for an optimally-sized CDS capacitor. While storing a voltage on the coupling capacitor also generates a reset noise, this reset noise is effectively reduce d by the feedback amplifier""s gain and the attenuation of the path from the storage node to the photodiode node. The feedback gain is nominally set to some multiple k of the reciprocal of the attenuation factor, i.e.:       A    V    ≈                    C        pJ                    C        fb              ⁢          (      k      )      
The present invention also eliminates feedthrough-induced offsets stemming from charge pumping. Applying feedback via the column buffer suppresses reset noise without having to implement correlated double sampling via on-chip or off-chip memory.
The low noise amplifier system of the present invention is formed by the aggregate circuitry in each pixel, and the waveform generation circuits and column buffers servicing that column or row of pixels. The signals from the active pixels are read out by the low-noise signal amplification system consisting of the active-pixel, the waveform generators and the column buffer. In addition to providing the means for suppressing the detector""s reset noise, the column buffer in the downstream electronics also may perform other typical functions, some of which are optional, including sample-and-hold, video pipelining, and column amplifier offset cancellation to suppress the temporal and spatial noise that would otherwise be generated by the column buffer.
The low-noise system provides the following key functions: (1) reset noise suppression using space-efficient analog memory in each pixel to facilitate reset noise suppression; (2) high sensitivity via source follower amplification; (3) adequate power supply rejection to enable development of cameras-on-a-chip that do not require elaborate support electronics; (4) compatibility with application to imaging arrays having pixel pitch less than 5 microns when using 0.25 xcexcm lithography; and (5) enables reasonable optical fill factors using lower cost 0.5 xcexcm lithography at 5 xcexcm pixel pitch.
The invention has the advantage of full process compatibility with standard silicided submicron CMOS, helps to maximize yield and minimize die cost because the circuit complexity is distributed among the active-pixels and peripheral circuits, and exploits the signal processing capability inherent to CMOS. The invention""s spectral response is broad from the near-ultraviolet (400 nm) to the near-IR ( greater than 800 nm).
Because the low-noise system of the present invention uses four MOSFETs, three of which are nearly minimum size, the invention offers as-drawn optical fill factor of approximately 12% at 7 xcexcm pixel pitch using 0.5 xcexcm design rules in the single-poly, three-metal CMOS available from many foundries. The actual optical fill factor is somewhat larger due to lateral collection and the large carrier diffusion length of commercial CMOS processes. Migrating the scheme to 0.25 xcexcm rules increases the fill factor to above 40%. A final advantage is the flexibility to collocate digital logic and signal-processing circuits due to the invention""s immunity to electromagnetic interference.
When fully implemented in the desired camera-on-a-chip architecture, the low-noise APS with fast reset can provide temporal read noise less than 15 exe2x88x92 at data rates compatible with either high frame rate video imaging or still photography via electronic means. It is also capable of minimizing fixed pattern noise to below 0.01% of the maximum signal (on a par with competing CCD imagers),  less than 0.5% nonlinearity, xcx9c1V signal swing for 3.3V power supply, large charge-handling capacity, and variable sensitivity using simple serial interface updated on a frame-by-frame basis via digital interface to a host microprocessor.